FPGA design and prototyping
   
 
Course Code: E03
Course Name: FPGA design and prototyping
Course Duration: 30 Hours
Course Fees: 1000 LE

Course Objectives:

  • Implement the VHDL portion of coding for synthesis .
    • Identify the differences between behavioral and structural coding styles
    • Distinguish coding for synthesis versus coding for simulation
    • Use scalar and composite data types to represent information
    • Use concurrent and sequential control structure to regulate information flow
    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures).
  • Simulate a basic VHDL design .
    • Write a VHDL testbench and identify simulation-only constructs .
  • Identify and implement coding best practices .
    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the ISE Design Suite environment.

Course Content:

  • State-of-the-Art Programmable Logic and FPGA Technology
  • FPGA vs. ASIC Designs
  • Introduction to VHDL language
  • Concurrent statement, components and Data Flow
  • Scalar and composite Data Types and operation
  • Sequential Design and simulation methodologies
  • Sequential statements, conditioning, looping, waiting
  • Basic Test bench
  • Finite State Machine
  • Design advanced Test bench
  • Building a Memory (distributed and blocked Memory)
  • Attributes, Functions and Procedures
  • Packages and Libraries
  • Design for synthesis

Course Prerequisites:

  • Fundamentals of electronics

Course Location:

Nasr City
Smart Village (Morning Only)

Available Times:

Morning (9am:3pm)
Evening

Course Dates:

2017-11-05